1. Field of the Invention:
The present invention relates generally to data synchronization and data error detection circuits and in particular to circuits in an asynchronous data reception device for synchronizing the transferred converted parallel word transmissions; i.e., serial to parallel data to the timing sequence of the data reception device during powerup and to circuits for detecting whether the transmitted parallel words sequence form a message usable by the reception device.
2. Prior Art
U.S. Pat. No. 4,885,583 dated Dec. 5, 1989 of the present inventor provides a circuit in an asynchronous device which converts serial data to parallel data and also flags out-of-range bits and framing errors. The present invention, as taught herein, may be used in cooperation with the structure claimed in this patent.
A problem exists when trying to power-up a bus receiver and have it extract data from messages broadcast asynchronously over a link intended for transceivers connected to the link. The bus receiver does not have means for informing the sender that the received messages contain overrange bits or that framing errors exist.
The bus receiver is essentially on its own in sorting out which messages are uncorrupted.
Also, in this system, each data message transfers as a three byte message preceded and succeeded by an idle byte. The bus receiver must get in synchronization with the transfer of each message so as to receive complete and not partial messages. The bus receiver must not only scrutinize the messages for errors but it must know when a data message contains too few or too many bytes.
To obtain the above-mentioned desiderata, a search for various means to synchronize receipt of asynchronously broadcast messages to the timing the receiver requires and at the same time scrutinize the data which was initiated. This search resulted in the power-up synchronization and error detection circuit of the present invention.